1. Field of the Invention
The present invention relates to a phase change memory device and a method for manufacturing a phase change memory device.
2. Related Art
A phase change memory device is a device having, as a memory cell, a phase change layer (chalcogenide semiconductor thin film or the like) offering electric resistance that changes depending on a crystalline state. The chalcogenide semiconductor is an amorphous semiconductor comprising a chalcogen element.
FIG. 23 is a diagram showing a part of a periodic table that is useful for describing chalcogen elements.
As shown in the figure, the chalcogen elements include S (sulfur), Se (selenium), and Te (tellurium), which belong to the VI-group elements. The applications of chalcogenide semiconductors are roughly classified into optical disks and electric memories. Known examples of the chalcogenide semiconductor used in the field of electric memories include GeSbTe (hereinafter referred to as GST), which is a compound of Ge (germanium), Te (tellurium), and Sb (antimony), AsSbTe, and SeSbTe.
FIGS. 24(a) and 24(b) are diagrams useful for explaining the principle of a phase change memory.
As shown in FIG. 24(a), the chalcogenide semiconductor can take on two stable states, non-crystalline state 10 and crystalline state 30. Transferring from non-crystalline state 10 to crystalline state 30 requires the supply of heat exceeding energy barrier 20.
As shown in FIG. 24(b), the non-crystalline state offers a high resistance, which is associated with a digital value “1”. The crystalline state offers a low resistance, which is associated with a digital value “0”. This enables digital information to be stored. Then, detecting a difference in the quantity of a current (or voltage drop) flowing via the chalcogenide semiconductor makes it possible to determine whether the stored information is “1” or “0”.
Joule heat is supplied to change the phase of the chalcogenide semiconductor. That is, the chalcogenide semiconductor is supplied with pulses having different peak values and different time widths to generate Joule heat in the vicinity of the interface between an electrode and the chalcogenide semiconductor. This Joule heat causes a phase change.
Specifically, the chalcogenide semiconductor is supplied with heat at a temperature close to its melting point for a short time and then rapidly cooled to become non-crystalline. On the other hand, the chalcogenide semiconductor is supplied with heat at a crystallization temperature lower than its melting point for a long time and is then cooled to become crystalline. For example, GST is supplied with heat at a temperature close to its melting point (about 610° C.) for a short time (1 to 10 ns) and then rapidly cooled (for about 1 ns) to become non-crystalline. On the other hand, GST is supplied with heat at a crystallization temperature (about 450° C.) for a long time (30 to 50 ns) and then cooled to become crystalline.
As shown in FIG. 24(b), transferring from the non-crystalline state to the crystalline state is called a “set” operation (crystallization process). The pulse applied to the chalcogenide semiconductor during the set operation is called a “set pulse”. Here, the minimum temperature required for crystallization (crystallization temperature) is defined as Tc. The minimum time required for crystallization (crystallization time) is defined as tr. On the contrary, transferring from the crystalline state to the non-crystalline state is called a “reset” operation (non-crystallization process). The pulse applied to the chalcogenide semiconductor during the reset operation is called a “reset pulse”. The heat applied to the chalcogenide semiconductor during the reset operation is at a temperature close to melting point Tm. The chalcogenide semiconductor is rapidly cooled after being melted.
FIGS. 25(a) to 25(d) are diagrams useful for describing the basic structure as well as a set operation and a reset operation of the phase change memory device.
As shown in FIG. 25(a), the phase change memory device basically has a chalcogenide semiconductor layer (phase change layer) 46 sandwiched between an upper electrode 48 and a lower electrode 42. Reference symbol 40 denotes a substrate. Reference symbol 44 denotes an electric insulating film. Upper electrode 48 connects to a terminal P to which the set pulse or the like is applied. Lower electrode 42 is fixed to a ground (reference potential).
As shown in FIG. 25(b), the phase change memory device in FIG. 25(a) is equivalent to a resistor R1. As described above, the resistance value of resistor R1 depends on whether the chalcogenide semiconductor is non-crystalline or crystalline. As shown in the left of FIG. 25(b), the following are input to terminal P: a set pulse S1 having a peak value exceeding a threshold voltage Vth, a reset pulse S2 having a larger peak value and a smaller width than S1, and a read pulse having a peak value of less than threshold voltage Vth and a larger width than S1. Here, reference symbol Vth denotes the lower limit voltage at which Joule heat required for crystallization can be generated.
FIG. 25(c) shows the correspondence between set pulse S1 and a rise in temperature caused by Joule heat generated by the supply of set pulse S1. The upper diagram shows a voltage waveform and the lower diagram shows how the temperature is raised by the Joule heat.
Set pulse S1 has a voltage value exceeding the predetermined threshold voltage Vth and a time width tcry. Time width tcry is equal to or longer than crystallization time tr, that is, the minimum time required to crystallize the chalcogenide semiconductor. The temperature reached under the effect of the Joule heat is considerably lower than melting point Tm and higher than the minimum temperature required for crystallization (crystallization temperature) Tc.
Similarly, FIG. 25(d) shows the correspondence between reset pulse S2 and a rise in temperature caused by Joule heat generated by the supply of reset pulse S2. The upper diagram shows a voltage waveform and the lower diagram shows how the temperature is raised by the Joule heat.
As shown in the figure, reset pulse S2 has a peak value significantly exceeding threshold voltage Vth for crystallization; the peak has a sufficient narrow width. The temperature reached under the effect of the Joule heat thus exceeds the melting point Tm of the chalcogenide semiconductor. A time width tamo from the peak temperature until the crystallization temperature Tc is sufficiently short. The chalcogenide semiconductor is thus melted and then rapidly cooled. As a result, the chalcogenide semiconductor returns to the non-crystalline state.
In the above description, a circuit scheme is used in which terminal P supplies set pulse S1 and reset pulse S2. However, such a circuit scheme as shown in FIG. 26 may be used.
FIG. 26 is a circuit diagram showing an example of a circuit scheme for the phase change memory device.
In FIG. 26, resistor R1 corresponds to the phase change memory device. Terminal P is connected to VDD (power-supply potential). Reference symbols M1 to M3 denote MOS transistors of an adjusted size. Reference symbols P1, P2, and P3 denote a set pulse terminal, a reset pulse terminal, and a read pulse terminal, respectively.
Terminals P1 to P3 are used to select which of MOS transistors M1 to M3 is to be turned on and to the time for which MOS transistors M1 to M3 are energized. This makes it possible to implement a set operation, a reset operation, and a read operation.
FIG. 27 is a circuit diagram useful for describing the read operation in the phase change memory device (phase change memory IC). In FIG. 27, the same components as those in FIG. 26 are denoted by the same reference symbols.
In FIG. 27, reference symbol W denotes a word line, reference symbol G denotes a ground line, and B denotes a bit line that is a pulse input line connected to terminal P to which set pulse S1, reset pulse S2, and read pulse S3 are input. Reference symbol R1 denotes the equivalent resistance of the phase change memory device comprising a chalcogenide semiconductor layer 60.
Reference symbol M4 denotes an NMOS transistor (switching element) for selecting a memory cell. Reference symbol R2 denotes a current/voltage converting resistor, and reference symbol A1 denotes a sense amplifier. Reference symbol 62 denotes a power-supply for supplying reference voltage to sense amplifier A1. Symbol I1 denotes a current flowing through a memory cell during a read operation. Reference symbol Vout denotes an output voltage (sensing output) from sense amplifier A1.
For a set operation (following description also applies to a reset operation and a read operation), word line W is set to an active level to turn on NMOS transistor M4. Subsequently, a required pulse (one of S1 to S3) is input to terminal P. For a read operation, read pulse S3 is input.
The resistance value of resistor R1 depends on whether chalcogenide semiconductor layer 60 comprised in a memory cell is non-crystalline or crystalline. The quantity of current 11 correspondingly varies. Accordingly, converting the current quantity into a voltage value and reading this value makes it possible to determine whether stored information is “1” or “0”.
FIGS. 28(a) and 28(b) are sectional views showing an example of conventional structure of a memory cell portion of the phase change memory device (phase change memory IC).
In FIG. 28(a), n+ layers 4a and 4b (source layer 4a and drain layer 4b) are formed in a p-type semiconductor substrate 2. A gate electrode 8 connected to word line W is disposed on a gate insulating film 6.
The n+ layer (source layer) 4a is connected to the ground potential via a ground plug 11 and a ground interconnection 12 both consisting of a highly conductive material such as tungsten (W).
Contact plugs 14 and 16 are formed on the n+ layer (drain layer) 4b. A heater electrode 18 is formed on contact plug 16.
The cross section area of heater electrode 18 is narrowed to increase current density so that Joule heat efficiently generates in a phase change region in a phase change layer 21.
Phase change layer 21 consisting of a chalcogenide semiconductor layer (GST or the like) is formed on heater electrode 18. Pulse input terminal P is connected to a top surface of phase change layer 21. Contact plugs 14 and 16 consist of, for example, tungsten (W). Heater electrode 18 consists of a high-resistance material, for example, titanium nitride (TiN). Contact plug 16 is interposed in order to prevent heat generated by heater electrode 18 from escaping to a semiconductor substrate.
The device in FIG. 28(a) has a 3-layer plug structure in which contact plugs 14, 16 and heater electrode 18 are stacked.
The basic configuration of the phase change memory shown in FIG. 28(b) is the same as that of the phase change memory device in FIG. 28(a). However, the phase change memory device in FIG. 28(b) has been eliminated contact plug 16, comprising tungsten (W). As a result, this phase change memory has a 2-layer plug structure in which contact plug 14 and heater electrode 18 are stacked.
A phase change memory having a 3-layer plug structure such as the one shown in FIG. 28(a) is described in, for example, Japanese Patent Laid-Open No. 2004-349504.
A phase change memory having a 2-layer plug structure such as the one shown in FIG. 28(b) is described in, for example, Japanese Patent Laid-Open No. 2005-244235.
The conventional phase change memory device requires at least 2-layer plug structure in which the contact plug and heater electrode are connected together. Completion of a memory cell in the phase change memory device requires more layers to be stacked.
That is, completion of a memory cell in the phase change memory device requires forming a phase change layer which is formed on the heater electrode, forming an upper electrode layer on the phase change layer, forming an interlayer insulating film on the phase change layer, forming a contact hole in the interlayer insulating film, burying a contact plug in the contact hole, and forming an electrode connected to the contact plug and corresponding to the bit line.
Consequently, the phase change memory device has a multilayer structure having at least three layers. This disadvantageously increases the size of the phase change memory device, complicates the device structure, and increases the number of manufacturing steps.
Connecting the plugs together so as to form multiple layers further increase the length of a current path, this thus causes an increased equivalent resistance.
Furthermore, the upper electrode comprising metal on the top surface of the phase change layer (chalcogenide layer) offers a high thermal conductivity and acts as a heat sink (radiating fin). This upper electrode thus allows Joule heat required for a phase change to escape. This correspondingly lowers the thermal efficiency of the phase change memory device. In other words, inhibiting the heat radiation from the upper electrode on the phase change layer enables the thermal efficiency of the phase change memory device to be improved.